(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming vias.
(2) Description of Prior Art
The fabrication of integrated circuit chips comprises the formation of semiconductor devices within the surface of a single crystalline silicon wafer, covering these devices with an insulative layer and forming contacts to the devices through openings in the insulative layer. These contacts are then further connected by a layer of patterned metallization which forms the wiring of basic circuits. Alternate levels of insulators and metallization connect the basic circuits to form a hierarchy of integrated circuit wiring which is finally brought to the external terminations of the chip.
A common practice is the use of conductive tungsten studs within the first insulating layer defining the contacts. These studs are connected to a first metallization level of an aluminum-copper(Al/Cu) alloy. An insulating layer is then formed over the patterned metallization, and openings are etched to allow the wiring pattern of a second metallization layer, also comprising an Al/Cu alloy, to connect to the wiring of the first. The second metal layer is deposited over the insulating layer and into the openings. Patterning and etching of the second metal layer completes the construction of the two interconnected wiring layers. The connections made by the second metal to the first metal through the openings in the insulator are generally referred to as vias.
Patterning of layers of all kinds is accomplished by etching away portions of a deposited layer leaving the desired wiring pattern in place. This selective removal always results in a non-planar surface. If steps were not taken to remove this non-planarity, the cumulative effect of patterning would quickly result in an unacceptable topography for proper metal coverage. Since the metal layers are deposited by non-conformal physical-vapor-deposition(PVD) techniques such as vacuum evaporation or sputtering, the general procedure is to planarize the insulator surface, at least locally, prior to the deposition of the next metal layer.
The configuration addressed by this invention is illustrated by FIG. 1. Shown here is a silicon wafer substrate 10 with semiconductor devices formed within its surface. The layer 14 represents a plurality of structural components layered beneath a metal layer 16. These comprise polysilicon levels which form components of MOS field-effect-transistors and their local interconnects. The figure illustrates two regions of interest on the wafer. In the left hand portion, the metal 16 lies over a region containing field oxide(FOX) 12 while in the right hand portion, the FOX layer is absent. The spaces 30 represents the patterning of the metal layer. Atop the metal layer 16 is a layer of titanium nitride 18 which is applied to provide an anti-reflective-coating(ARC) over the metal layer 16. This coating serves to eliminate reflections from the metal surface during exposure of the patterning photoresist.
An insulative layer 20 is deposited over the patterned metal layer 16. This layer, referred to as an inter-metal dielectric(IMD) layer, is deposited thicker than required and is subsequently planarized by any of several commonly known techniques. For this illustration, chemical-mechanical-polishing(CMP) may be used. This method provides a global planarization of the wafer surface. After planarization, the IMD is thinner over the section which lies over the field oxide 12.
Photoresist 22 is applied and patterned to define vias 32 and 34 for the connections to the next metal level. The vias are etched by reactive-ion-etching(RIE) exposing the TiN ARC layer.
The ARC layer 18 could provide an effective etch stop providing the etch-rate selectivity for the silicon oxide IMD dielectric 20 over the TiN were great enough. However, this is not the case. Consequently, in order to complete the opening of the deep via 34, the shallow via 32 must be over etched to such an extent that the ARC layer is penetrated and a portion of the Al/Cu metal layer is lost.
Since a greater selectivity cannot be obtained, one approach to this problem would be to make the TiN layer 18 thicker so that the over-etch of the shallow via 32 required to open the deep via 34 terminates within the TiN layer. However, since the resistivity of TiN is over an order of magnitude greater than that of the AlCu alloy, the R.sub.c of the via would be adversely affected.
An additional consequence of Al/Cu penetration in the shallow via 32 is a deterioration of metal edge coverage by the deposited via metal. However, this shortcoming is also experienced in the deep via 34.
Sandhu et.al. U.S. Pat. No. 5,258,096 describe the usage of etch stop layers for forming contacts and vias of varying depths. They mention the use of several materials including doped polysilicon, Ti, and TiN. In their invention they use a doped polysilicon layer which is deposited solely to be locally formed into etch stops for contact access openings in a DRAM array structure and its periphery. Their process requires a separate deposition step to form the doped polysilicon layer which makes direct contact to the device active regions. The modification ARC layers to be used as etch stops is not suggested.
Chen U.S. Pat. No. 5,462,895 forms a layer of varying composition, beginning as a Ti enriched layer of TiN which is continuously blended into a stoichiometric TiN layer. A continuous chemical-vapor-deposition(CVD) process is used for the deposition. This layer performs as an adhesive layer between a silicon contact and a tungsten plug. The Ti rich portion forms a TiSi.sub.x bond with the silicon in the contact. The layer is not called upon to block a subsequent etch.